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2006 Microchip Technology Inc.

Preliminary

DS70178C-page 215

dsPIC30F1010/202X

18.9.2

IDLE MODE

In Idle mode, the clock to the CPU is shutdown while

peripherals keep running. Unlike Sleep mode, the clock

source remains active.

Several peripherals have a control bit in each module

that allows them to operate during Idle.

LPRC fail-safe clock remains active if clock failure

detect is enabled.

The processor wakes up from Idle if at least one of the

following conditions is true:

on any interrupt that is individually enabled (IE bit

is ‘1’) and meets the required priority level

on any Reset (POR, MCLR)

on WDT time-out

Upon wake-up from Idle mode, the clock is reapplied to

the CPU and instruction execution begins immediately,

starting with the instruction following the PWRSAV

instruction.

Any interrupt that is individually enabled (using IE bit)

and meets the prevailing priority level will be able to

wake-up the processor. The processor will process the

interrupt and branch to the ISR. The Idle status bit in

RCON register is set upon wake-up.

Any Reset, other than POR, will set the Idle status bit.

On a POR, the Idle bit is cleared.

If Watchdog Timer is enabled, then the processor will

wake-up from Idle mode upon WDT time-out. The Idle

and WDTO status bits are both set.

Unlike wake-up from Sleep, there are no time delays

involved in wake-up from Idle.

18.10 Device Configuration Registers

The Configuration bits in each device Configuration

programmed by a device programmer, or by using the

In-Circuit Serial Programming (ICSP) feature of the

device. Each device Configuration register is a 24-bit

used to hold configuration data. There are six

Configuration registers available to the user:

FBS (0xF80000): Boot Code Segment

Configuration Register

FGS (0xF80004): General Code Segment

Configuration Register

FOSCEL (0xF80006): Oscillator Selection

Configuration Register

FOSC (0xF80008): Oscillator Configuration

FWDT (0xF8000A): Watchdog Timer

Configuration Register

FPOR (0xF8000C): Power-On Reset

Configuration Register

The placement of the Configuration bits is automati-

cally handled when you select the device in your device

programmer. The desired state of the Configuration bits

may be specified in the source code (dependent on the

language tool used), or through the programming

interface. After the device has been programmed, the

application software may read the Configuration bit

values through the table read instructions. For addi-

tional information, please refer to the programming

specifications of the device.

Table 18-5 shows the bit descriptions of the FGS and

FBS registers for the dsPIC30F1010. Table 18-6

shows the bit descriptions of the FGS and FBS regis-

ters for dsPIC30F202x devices. Table 18-7 shows the

bit descriptions of FWDT and the FPOR registers for

dsPIC30F1010/202X devices.

Note:

If the code protection configuration fuse

bits (GSS<1:0> and GWRP in the FGS

erase of the entire code-protected device

is only possible at voltages VDD

≥ 4.5V.

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